🎟️ Cambridge Wireless members can get 20% discount by using the code: Cw20%Dc

Formal Verification is a powerful technique for proving the correctness of digital designs beyond what traditional simulation can achieve. This intensive, hands-on training is designed to upskill engineers in real-world verification strategies, with practical tips and methodologies drawn from over 30 years of industry experience.

👥 Who Should Attend:

• Engineers and verification professionals working with Verilog, SystemVerilog, or VHDL.

• Participants with prior digital design experience seeking to enhance verification efficiency and confidence.

💡 Key Takeaways:

By the end of the course, you will be able to:

• Understand and apply core formal verification principles.

• Write and prove properties for digital blocks and SoCs.

• Analyse coverage and assess verification quality.

• Apply practical tips to improve verification productivity immediately.

🛠️ Agenda Highlights:

• Introduction to SystemVerilog Assertions (SVA).

• Writing basic and advanced properties.

• Debugging failing properties.

• Measuring coverage and completeness.

• Full formal verification of a design block.

• Formal verification applications in the design flow.

Format: Hybrid (In-person at San Jose, CA or Live Online)

Duration: Full-Day Training (12:00 PM - 7:00 PM PDT)

To secure your spot, please register on our ticket page:

👉   [Click here to register on Ticket Tailor]